The present invention relates to a semiconductor device, and more specifically, for example, to a semiconductor device including a data transfer function.
A single-chip microcomputer, as described in the “LSI Handbook”, pp. 540-541, published by Ohmsha Ltd., on Nov. 30, 1384, generally consists of a central processing unit (CPU) and other functional blocks including a read only memory (ROM) for program storage, a random access memory (RAM) for data storage, and an input/output circuit for input and output of data or signals, with all of these blocks formed on a single semiconductor substrate. The single-chip microcomputer is used to control equipment.
In the control of equipment of the single-chip microcomputer described above, a data transfer may be performed in response to en event such as an interrupt. When the central processing unit (CPU) performs interrupt processing, exception processing, operations of saving to a stack/recovering from a stack, and execution of a recovery instruction are required to switch the process flow. However, the processing of the central processing unit (CPU) requires processing of saving to a stack/recovering from a stack. Further, in the processing of the central processing unit (CPU), a time for an operation such as instruction reading among processing required for the data transfer processing tends to increase.
In view of the problems of the data transfer by the central processing unit (CPU) described above, a technique of providing a data transfer apparatus which is a hardware different from the central processing unit (CPU) in a microcomputer has been suggested. A microcomputer disclosed in Japanese Unexamined Patent Application Publication No. 1-125644 (Hayashi) includes a data transfer apparatus therein. This data transfer apparatus achieves a data transfer in response to a request from a large a under of peripheral processing devices (input/output circuit) with less hardware. The microcomputer disclosed in Hayashi includes a storage device (RAM) that stores data transfer information including a transfer source address indicating the location in a memory which stores data to be transferred. Further, the microcomputer includes a vector table that holds storage addresses in a storage device (RAM) of all the information required for the data transfer. The data transfer apparatus includes means for referring to the vector table upon receiving a data transfer start request, and means for acquiring information required for the data transfer from the vector table. Hayashi mainly teaches performing a data transfer with less hardware and does not teach specific details of the data transfer.
Japanese Unexamined Patent Application Publication No. 2000-194647 (Yamashita) discloses a configuration in which an arithmetic operation unit is provided in a data transfer apparatus. The arithmetic operation unit performs a comparison and a simple arithmetic operation of data that is set in advance and data to be transferred. According to the comparison results of data, the data transfer apparatus does not perform a predetermined number of data transfer operations, and requests a central processing unit (CPU) to execute processing.
A data transfer apparatus disclosed in Japanese Unexamined Patent Application Publication No. 7-129537 (Mitsuishi) executes reading from a storage device storing information required for a data transfer to execute a plurality of successive data transfer operations. This technique is also called a chain transfer. According to this technique, the data transfer apparatus is able to execute an arbitrary number of data transfer operations according to a start factor of the data transfer, and can be used for various applications. Further, due to the chain operation, the flexibility of the whole system can be improved. The data transfer apparatus disclosed by Mitsuishi is able to execute a repeat transfer mode and a data block transfer mode.
As described above, the microcomputer includes a dedicated hardware (data transfer apparatus) that performs a data transfer. It is therefore possible to achieve a high-speed data transfer compared to the case in which the central processing unit (CPU) performs a data transfer. Further, since the data transfer apparatus performs data transfer, the frequency of processing in the central processing unit (CPU) decreases. Since the frequency of the interrupt processing decreases, the overhead of processing such as transition/recovery decreases. This enables the microcomputer to achieve efficient processing. The data transfer apparatus has a logical size smaller than that of the central processing unit (CPU). Accordingly, when the data transfer apparatus performs the data transfer, power consumption can be suppressed compared to the case in which the central processing unit (CPU) performs the data transfer.
In recent years, the number of functions implemented in a microcomputer has been increasing. As the number of functions increases, the number of data transfer operations that should be performed in response to an event such as an interrupt increases as well. Further, when other accompanying operations can be executed at the time of data transfer, the processing efficiency can further be improved. It is therefore required to enhance the functionality of the data transfer apparatus, and to reduce the processing load of the central processing unit (CPU). Related arts regarding the enhancement of the functionality of the data transfer apparatus includes Japanese Unexamined Patent Application Publication No. 6-318183 (Owaki at al.), Japanese Unexamined Patent Application Publication No. 2012-155604 (Matsuzawa), and Japanese Unexamined Patent Application Publication No. 2005-301665 (Azumaya).
Owaki et al., discloses a DMA controller that determines input data input from a first memory using a control signal, processes the data according to the determination, and then writes the processed data into a second memory. Matsuzawa discloses a data transfer control device that performs arithmetic operation processing of transfer data in a DMA transfer between a system memory and a large-capacity memory of a digital camera. Azumaya discloses a data processing apparatus that performs arithmetic operation processing of transfer data when data is transferred from a memory by a DMA method.